Course Content and Outcomes Guides (CCOG)

CCOG for ENGR 271 archive revision 201604

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Effective Term:
Fall 2016 through Winter 2025

Course Number:
ENGR 271
Course Title:
Digital Logic Design
Credit Hours:
4
Lecture Hours:
30
Lecture/Lab Hours:
0
Lab Hours:
30

Course Description

Explores shift register devices and circuits; design, timing analysis, and application of synchronous state machine circuits using discrete devices and programmable logic devices. Includes timing analysis of asynchronous state machines, arithmetic circuits and devices; internal architecture of a microprocessor; design and interfacing of memory systems. Introduces design for test techniques. Reinforces the systematic design methodology, documentation standards, and use of computer-based tools. Audit available.

Intended Outcomes for the course

Upon completion of the course students should be able to:

  1. Realize complex logic functions utilizing programmable logic.
  2. Design machines for the purpose of manipulating data streams.
  3. Design complex digital systems.

Course Activities and Design

Course activities will include lecture presentations, coordinated homework and laboratory assignments, and examinations.

Outcome Assessment Strategies

Student evaluation includes examinations, laboratory assignments, homework assignments, and a final comprehensive examination. Specific evaluation procedures will be discussed during the first class meeting.

Course Content (Themes, Concepts, Issues and Skills)

  • Bistable Elements, Latches, Flip-Flops

  • Clocked Synchronous State-Machine Analysis

  • Moore and Mealy Architectures

  • Clocked Synchronous State-Machine Design

  • Design Using Transition Lists

  • Feedback Sequential Circuit Analysis

  • Feedback Sequential Circuit Design

  • Sequential Circuit Design with HDL

  • Sequential Circuit Design Standards

  • Sequential PLDs

  • Counters and Shift Registers

  • Specialized Shift-Registers

  • Iterative vs Sequential Circuits

  • Impediments to Synchronous Design

  • Syncronizer Failure and Metastability

  • Memories Architectures and Devices